Magnitude and phase angle of complex signal (2024)

magAngle = dsphdl.ComplexToMagnitudeAngle returns a dsphdl.ComplexToMagnitudeAngle System object, magAngle, that computes the magnitude and phase angle of a complex input signal.

example

example

[mag,angle,validOut]= magAngle(X,validIn) converts a scalar or vector of complex values X into their component magnitude and phase angles. validIn and validOut are logical scalars that indicate the validity of the input and output signals, respectively.

The CORDIC algorithm is a hardware-friendly method for performing trigonometric functions. It is an iterative algorithm that approximates the solution by converging toward the ideal point. The object uses CORDIC vectoring mode to iteratively rotate the input onto the real axis.

The Givens method for rotating a complex number x+iy by an angle θ is as follows. The direction of rotation, d, is +1 for counterclockwise and −1 for clockwise.

For a hardware implementation, factor out the cosθ to leave a tanθ term.

To rotate the vector onto the real axis, choose a series of rotations of θ_n so that $$\tan {\theta }_n=2^{-n}$$. Remove the cosθ term so each iterative rotation uses only shift and add operations.

Combine the missing cosθ terms from each iteration into a constant, and apply it with a single multiplier to the result of the final rotation. The output magnitude is the scaled final value of x. The output angle, z, is the sum of the rotation angles.

The convergence region for the standard CORDIC rotation is ≈±99.7°. To work around this limitation, before doing any rotation, the object maps the input into the [0,π/4] range using the following algorithm.

if abs(x) > abs(y) input_mapped = [abs(x), abs(y)];else input_mapped = [abs(y), abs(x)];end

At each iteration, the object rotates the vector towards the real axis. The rotation is counterclockwise when y is negative, and clockwise when y is positive.

Quadrant mapping saves hardware resources and reduces latency by reducing the number of CORDIC pipeline stages by one. The CORDIC gain factor, Kn, therefore does not include the n=0, or cos(π/4) term.

After the CORDIC iterations are complete, the object corrects the angle back to its original location. First it adjusts the angle to the correct side of π/4.

if abs(x) > abs(y) angle_unmapped = CORDIC_out;else angle_unmapped = (pi/2) - CORDIC_out;end

Then it flips the angle to the original quadrant.

if (x < 0) if (y < 0) output_angle = - pi + angle_unmapped;e else output_angle = pi - angle_unmapped;else if (y<0) output_angle = -angle_unmapped;

The object generates a pipelined HDL architecture to maximize throughput. Each CORDIC iteration is done in one pipeline stage. The gain multiplier, if enabled, is implemented with Canonical Signed Digit (CSD) logic.

If you use vector input, this object replicates this architecture in parallel for each element of the vector.

The CORDIC logic at each pipeline stage implements one iteration. For each pipeline stage, the shift and angle rotation are constants.

When you set OutputFormat to 'Magnitude', the object does not generate HDL code for the angle accumulation and quadrant correction logic.

This format normalizes the fixed-point radian angle values around the unit circle. This is a more efficient use of bits than a range of [0,2π] radians. Normalized angle format also enables wraparound at 0/2π without additional detect and correct logic.

For example, representing the angle with 3 bits results in the following normalized values.

Using the mapping described in Modified CORDIC Algorithm, the object normalizes the angles across [0,π/4] and maps them to the correct octant at the end of the calculation.

The latency is NumIterations + 4 cycles from input to output. Each call to the object models one clock cycle.

When you set NumIterationsSource to 'Auto', the number of iterations is one less than the input word length and the latency is three more than the input word length. If the data type of the input is double or single, the number of iterations is 16 and the latency is 20.

Performance was measured for the default configuration, with output scaling disabled and fixdt(1,16,12) input. When the generated HDL code is synthesized into a Xilinx^® ZC706 (XC7Z045FFG900-2) FPGA, the design achieves 350 MHz clock frequency. It uses the following resources.

When you use a multiplier for the CORDIC gain scaling, the design uses one DSP block and has a shorter critical path. The critical path difference is not significant at this number of bits, but as the size of the data increases, the critical path of the CSD implementation rises faster than the critical path of the multiplier.

Performance of the synthesized HDL code varies depending on your target and synthesis options. When you use vector input, the resource usage is about VectorSize times the scalar resource usage.